1. Field of the Invention
The present application generally relates to a scheduler and more particularly to a scheduler for a Direct Memory Access (DMA) device having multiple channels.
2. Description of the Related Art
In general, the Direct Memory Access (DMA) of a device controls the transfer of data between peripheral devices and the memory of the device. The device may include an input DMA and an output DMA to service data received from peripheral devices and data sent to peripheral devices, respectively. When a peripheral device wants to send data to a device with an input DMA, the peripheral device sends a request to the input DMA. The input DMA can then send an Acknowledgement (ACK) to the peripheral. When the peripheral device receives the ACK, it transfers data to the input DMA, which then transfers the data into memory. When data is to be sent out to a peripheral device, the processor of the device sends a request to the output DMA. The output DMA then retrieves data from memory and sends it out to the peripheral device.
Conventional DMAs typically have multiple channels that can be connected to multiple peripherals, multiple channels on one peripheral, or to multiple memory channels on the device. Conventional DMAs also typically have arbitrators or schedulers to control these multiple channels. However, as the number of channels on DMAs has increased, the complexity of these arbitrators/schedulers has also increased. This can increase the cost and reduced the processing speed of the DMA.